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November 2006
HYS64T32000HM-[3S/3.7/5]-A HYS64T64020HM-[3S/3.7/5]-A
214-Pin Micro-DIMM-DDR2-SDRAM Modules MDIMM DDR2 SDRAM RoHS Compliant
Internet Data Sheet
Rev. 1.11
Internet Data Sheet
HYS64T[32/64]0[0/2]0HM-[3S/3.7/5]-A Micro-DIMM DDR2 SDRAM Modules
HYS64T32000HM-[3S/3.7/5]-A, HYS64T64020HM-[3S/3.7/5]-A Revision History: 2006-11, Rev. 1.11 Page All All All Subjects (major changes since last revision) Qimonda update Adapted internet edition Added -3S
Previous Revision: 2005-10, Rev. 1.1 Previous Revision: 2004-10, 1.0
We Listen to Your Comments Any information within this document that you feel is wrong, unclear or missing at all? Your feedback will help us to continuously improve the quality of this document. Please send your proposal (including a reference to this document) to: techdoc@qimonda.com
qag_techdoc_rev400 / 3.2 QAG / 2006-08-07 03062006-HT1R-Z2PY
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Internet Data Sheet
HYS64T[32/64]0[0/2]0HM-[3S/3.7/5]-A Micro-DIMM DDR2 SDRAM Modules
1
Overview
This chapter gives an overview of the 1.8 V 214-Pin Micro-DIMM-DDR2-SDRAM Modules product family and describes its main characteristics.
1.1
Features
* Burst Refresh, Distributed Refresh and Self Refresh * All inputs and outputs SSTL_1.8 compatible * Off-Chip Driver Impedance Adjustment (OCD) and On-Die Termination (ODT) * Serial Presence Detect with E2PROM * MDIMM Dimensions (nominal): 30 mm high, 54.0 mm wide * Based on standard reference layouts Raw Cards: "A" and "B" * 2-piece type Mezzanine Socket with 0,4 mm contact centers * RoHS Compliant Products1)
* 214-Pin PC2-5300, PC2-4200 and PC2-3200 DDR2 SDRAM memory modules for use as main memory when installed in systems such as mobile personal computers. * 32M x 64and 64M x 64 module organization, and 32M x 16 chip organization * Standard Double-Data-Rate-Two Synchronous DRAMs (DDR2 SDRAM) with a single + 1.8 V ( 0.1 V) power supply * 256MB and 512MB modules built with 512Mb DDR2 SDRAMs in P-TFBGA-84 chipsize packages * Programmable CAS Latencies (3, 4 and 5), Burst Length (8 & 4) and Burst Type
TABLE 1
Performance Table
Product Type Speed Code Speed Grade Max. Clock Frequency @CL5 @CL4 @CL3 Min. RAS-CAS-Delay Min. Row Precharge Time Min. Row Active Time Min. Row Cycle Time -3S PC2-5300 5-5-5 -3.7 PC2-4200 4-4-4 266 266 200 15 15 45 60 -5 PC2-3200 3-3-3 200 200 200 15 15 40 55 Unit -- MHz MHz MHz ns ns ns ns
fCK5 fCK4 fCK3 tRCD tRP tRAS tRC
333 266 200 15 15 45 60
1) RoHS Compliant Product: Restriction of the use of certain hazardous substances (RoHS) in electrical and electronic equipment as defined in the directive 2002/95/EC issued by the European Parliament and of the Council of 27 January 2003. These substances include mercury, lead, cadmium, hexavalent chromium, polybrominated biphenyls and polybrominated biphenyl ethers.
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Internet Data Sheet
HYS64T[32/64]0[0/2]0HM-[3S/3.7/5]-A Micro-DIMM DDR2 SDRAM Modules
1.2
Description
capacitors are mounted on the PCB board. The DIMMs feature serial presence detect based on a serial E2PROM device using the 2-pin I2C protocol. The first 128 bytes are programmed with configuration data and are write protected; the second 128 bytes are available to the customer.
The QIMONDA HYS64T[32/64]0[0/2]0HM-[3S/3.7/5]-A module family are Unbuffered Micro-DIMM modules "MDIMMs" with 30 mm height based on DDR2 technology. DIMMs are available as non-ECC modules in 32M x 64 (256 MB) and 64M x 64 (512 MB) organization and density, intended for mounting into 214-pin mezzanine connector sockets. The memory array is designed with 512-Mbit Double-DataRate-Two (DDR2) Synchronous DRAMs. Decoupling
TABLE 2
Ordering Informationfor RoHS Compliant Products
Product Type1) PC2-5300 HYS64T32000HM-3S-A HYS64T64020HM-3S-A PC2-4200 HYS64T32000HM-3.7-A HYS64T64020HM-3.7-A PC2-3200 HYS64T32000HM-5-A HYS64T64020HM-5-A 256MB 1Rx16 PC2-3200M-333-12-B1 512MB 2Rx16 PC2-3200M-333-12-A1 1 rank, Non-ECC 2 ranks, Non-ECC 512 Mbit (x16) 512 Mbit (x16) 256MB 1Rx16 PC2-4200M-444-12-B1 512MB 2Rx16 PC2-4200M-444-12-A1 1 rank, Non-ECC 2 ranks, Non-ECC 512 Mbit (x16) 512 Mbit (x16) 256MB 1Rx16 PC2-5300M-555-12-B1 512MB 2Rx16 PC2-5300M-555-12-A1 1 rank, Non-ECC 2 ranks, Non-ECC 512 Mbit (x16) 512 Mbit (x16) Compliance Code2) Description SDRAM Technology
1) All Product Type numbers end with a place code, designating the silicon die revision. Example: HYS64T32000HM-3.7-A, indicating Rev. "A" dies are used for DDR2 SDRAM components. For all QIMONDA DDR2 module and component nomenclature see Chapter 6 of this data sheet. 2) The Compliance Code is printed on the module label and describes the speed grade, for example "PC2-4200M-444-12-B1", where 4200M means Unbuffered Micro-DIMM modules with 4.26 GB/sec Module Bandwidth and "444-11" means Column Address Strobe (CAS) latency = 4, Row Column Delay (RCD) latency = 4 and Row Precharge (RP) latency = 4 using the latest JEDEC SPD Revision 1.2 and produced on the Raw Card "B".
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Internet Data Sheet
HYS64T[32/64]0[0/2]0HM-[3S/3.7/5]-A Micro-DIMM DDR2 SDRAM Modules
TABLE 3
Address Format
DIMM Density 256 MByte 512 MByte Module Organization 32M x64 64M x64 Memory Ranks 1 2 ECC/ Non-ECC Non-ECC Non-ECC # of SDRAMs 4 8 # of row/bank/columns bits 13/2/10 13/2/10 Raw Card B A
TABLE 4
Components on Modules
Product Type1) HYS64T32000HM HYS64T64020HM DRAM Components1) HYB18T512160AF HYB18T512160AF DRAM Density 512 Mbit 512 Mbit DRAM Organisation Note2) 32M x16 32M x16
1) Green Product 2) For a detailed description of all functionalities of the DRAM components on these modules see the component data sheet.
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Internet Data Sheet
HYS64T[32/64]0[0/2]0HM-[3S/3.7/5]-A Micro-DIMM DDR2 SDRAM Modules
2
2.1
Pin Configuration
Pin Configuration
This chapter contains the pin configuration.
The pin configuration of the DDR2 SDRAM Micro-DIMM is listed by function in Table 5 (214 pins). The abbreviations used in columns Pin and Buffer Type are explained in Table 6 and Table 7 respectively. The pin numbering is depicted in Figure 1.
TABLE 5
Pin Configuration of MDIMM
Ball No. Clock Signals 122 194 123 195 43 147 CK0 CK1 CK0 CK1 CKE0 CKE1 NC Control Signals 165 62 S0 S1 NC 163 60 56 55 162 46 RAS CAS WE BA0 BA1 BA2 NC I I NC I I I I I I NC SSTL SSTL SSTL SSTL SSTL - Bank Address Bus 2 Note: Greater than 512Mb DDR2 SDRAMS Not Connected Note: Less than 1Gb DDR2 SDRAMS Bank Address Bus 1:0 SSTL SSTL Chip Select Rank 1:0 Note: 2-rank module. Not Connected Note: 1-rank module Row Address Strobe (RAS), Column Address Strobe (CAS), Write Enable (WE) I I I I I I NC SSTL SSTL SSTL SSTL SSTL SSTL Clock Enables 1:0 Note: 2-rank module Not Connected Note: 1-rank module Clock Signal CK 1:0, Complementary Clock Signal CK 1:0 Name Pin Type Buffer Type Function
Address Signals
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Internet Data Sheet
HYS64T[32/64]0[0/2]0HM-[3S/3.7/5]-A Micro-DIMM DDR2 SDRAM Modules
Ball No. 161 159 52 158 51 50 157 48 155 154 54 47 153 167
Name A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 AP A11 A12 A13 NC
Pin Type I I I I I I I I I I I I I I I NC
Buffer Type SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL -
Function Address Inputs 12:0, Address Input 10/Autoprecharge
Address Input 13 Note: Modules based on x4/x8 component Not Connected Note: Modules based on x16 component Data Bus 0:38 Note: Data Input/Output pins
Data Signals 3 4 9 10 109 110 114 115 12 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 I/O I/O I/O I/O I/O I/O I/O I/O I/O SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL
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Internet Data Sheet
HYS64T[32/64]0[0/2]0HM-[3S/3.7/5]-A Micro-DIMM DDR2 SDRAM Modules
Ball No. 13 21 22 117 118 125 126 24 25 30 31 128 129 133 134 33 34 38 39 136 137 142 143 67 68 73 74 174 175 179 180 76 77 81 82 182 183 188 189 84
Name DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ48
Pin Type I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O
Buffer Type SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL
Function Data Bus 0:38 Note: Data Input/Output pins
Data Bus 39:57
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HYS64T[32/64]0[0/2]0HM-[3S/3.7/5]-A Micro-DIMM DDR2 SDRAM Modules
Ball No. 85 92 93 191 192 200 201 95 96 101 102 203 204 208 209 7 6 19 18 28 27 140 139 71 70 186 185 198 197 99 98 112 120 131 36 177 79 90 206
Name DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 DQS0 DQS0 DQS1 DQS1 DQS2 DQS2 DQS3 DQS3 DQS4 DQS4 DQS5 DQS5 DQS6 DQS6 DQS7 DQS7 DM0 DM1 DM2 DM3 DM4 DM5 DM6 DM7
Pin Type I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I I I I I I I I
Buffer Type SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL
Function Data Bus 39:57
Data Strobes 7:0
Data Masks 7:0 Note: x8 based module
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HYS64T[32/64]0[0/2]0HM-[3S/3.7/5]-A Micro-DIMM DDR2 SDRAM Modules
Ball No. EEPROM 105 104 211 213 Power Supplies 1 42, 45, 49, 53, 57, 61, 64, 146, 149, 152, 156, 160, 164, 168, 171 107 2, 5, 8, 11, 14, 17, 20, 23, 26, 29, 32, 35, 37, 40, 66, 69, 72, 75, 78, 80, 83, 86, 89, 91, 94, 97, 100, 103, 108, 111, 113, 116, 119, 121, 124, 127, 130, 132, 135, 138, 141, 144, 173, 176, 178, 181, 184, 187, 190, 193, 196, 205, 199, 202, 207, 210 Other Pins 166 63
Name
Pin Type I I/O I I AI PWR
Buffer Type CMOS OD CMOS CMOS - -
Function
SCL SDA SA0 SA1
Serial Bus Clock Serial Bus Data Serial Address Select Bus 1:0
VREF VDD
I/O Reference Voltage Power Supply
VDDSPD VSS
PWR GND
- -
EEPROM Power Supply Ground Plane
ODT0 ODT1 NC
I I
SSTL SSTL
On-Die Termination Control 1:0 Note: 2-rank module On-Die Termination Control 1:0 Note: 2-rank module Not Connected Note: 1-rank module
15, 16, 41, 44, 46, 58, 59, 65, 87, 88, 106, 145, 148, 150, 151, 167, 169, 170, 172, 212, 214
NC
NC
Not connected
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HYS64T[32/64]0[0/2]0HM-[3S/3.7/5]-A Micro-DIMM DDR2 SDRAM Modules
TABLE 6
Abbreviations for Pin Type
Abbreviation I O I/O AI PWR GND NC Description Standard input-only pin. Digital levels. Output. Digital levels. I/O is a bidirectional input/output signal. Input. Analog levels. Power Ground Not Connected
TABLE 7
Abbreviations for Buffer Type
Abbreviation SSTL CMOS OD Description Serial Stub Terminated Logic (SSTL_18) CMOS Levels Open Drain. The corresponding pin has 2 operational states, active low and tristate, and allows multiple devices to share as a wire-OR.
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HYS64T[32/64]0[0/2]0HM-[3S/3.7/5]-A Micro-DIMM DDR2 SDRAM Modules
FIGURE 1
Pin Configuration for Two-Piece Mezzanine Socket on MDIMM (214 pins)
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HYS64T[32/64]0[0/2]0HM-[3S/3.7/5]-A Micro-DIMM DDR2 SDRAM Modules
3
3.1
Electrical Characteristics
Absolute Maximum Ratings
TABLE 8
Absolute Maximum Ratings
This chapter lists the electrical characteristics.
Caution is needed not to exceed absolute maximum ratings of the DRAM device listed in Table 8 at any time.
Symbol
Parameter
Rating Min. Max. +2.3 +2.3 +2.3 +2.3
Unit
Note
Storage Temperature -55 +100 1) When VDD and VDDQ and VDDL are less than 500 mV; VREF may be equal to or less than 300 mV.
2) Storage Temperature is the case surface temperature on the center/top side of the DRAM.
VDD VDDQ VDDL VIN, VOUT TSTG
Voltage on VDD pin relative to VSS Voltage on VDDQ pin relative to VSS Voltage on VDDL pin relative to VSS Voltage on any pin relative to VSS
-1.0 -0.5 -0.5 -0.5
V V V V C
1) 1)2) 1)2) 1) 1)2)
Attention: Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
TABLE 9
DRAM Component Operating Temperature Range
Symbol Parameter Rating Min. Max. 95 C
1)2)3)4)
Unit
Note
TOPER
Operating Temperature
0
1) Operating Temperature is the case surface temperature on the center / top side of the DRAM. 2) The operating temperature range are the temperatures where all DRAM specification will be supported. During operation, the DRAM case temperature must be maintained between 0 - 95 C under all other specification parameters. 3) Above 85 C the Auto-Refresh command interval has to be reduced to tREFI= 3.9 s 4) When operating this product in the 85 C to 95 C TCASE temperature range, the High Temperature Self Refresh has to be enabled by setting EMR(2) bit A7 to "1". When the High Temperature Self Refresh is enabled there is an increase of IDD6 by approximately 50%
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HYS64T[32/64]0[0/2]0HM-[3S/3.7/5]-A Micro-DIMM DDR2 SDRAM Modules
3.2
DC Operating Conditions
TABLE 10
Operating Conditions
This chapter contains the DC operating conditions tables.
Parameter
Symbol
Values Min. Max. +65 +95 +100 +105 90
Unit
Note
Operating temperature (ambient) DRAM Case Temperature Storage Temperature Barometric Pressure (operating & storage) Operating Humidity (relative)
1) 2) 3) 4)
TOPR TCASE TSTG
PBar
0 0 - 50 +69 10
C C C kPa %
5) 1)2)3)4)
HOPR
DRAM Component Case Temperature is the surface temperature in the center on the top side of any of the DRAMs. Within the DRAM Component Case Temperature Range all DRAM specifications will be supported Above 85 C DRAM Case Temperature the Auto-Refresh command interval has to be reduced to tREFI = 3.9 s When operating this product in the 85 C to 95 C TCASE temperature range, the High Temperature Self Refresh has to be enabled by setting EMR(2) bit A7 to "1". When the High Temperature Self Refresh is enabled there is an increase of IDD6 by approximately 50%. 5) Up to 3000 m.
TABLE 11
Supply Voltage Levels and DC Operating Conditions
Parameter Symbol Values Min. Device Supply Voltage Output Supply Voltage Input Reference Voltage SPD Supply Voltage DC Input Logic High DC Input Logic Low Typ. 1.8 1.8 0.5 x VDDQ -- -- -- Max. 1.9 1.9 0.51 x VDDQ 3.6 V V V V V V
3) 1) 2)
Unit
Note
In / Output Leakage Current -5 -- 5 A 1) Under all conditions, VDDQ must be less than or equal to VDD 2) Peak to peak AC noise on VREF may not exceed 2% VREF (DC).VREF is also expected to track noise in VDDQ. 3) Input voltage for any connector pin under test of 0 V VIN VDDQ + 0.3 V; all other pins at 0 V. Current is per pin
VDD VDDQ VREF VDDSPD VIH(DC) VIL (DC) IL
1.7 1.7 0.49 x VDDQ 1.7
VREF + 0.125
- 0.30
VDDQ + 0.3 VREF - 0.125
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HYS64T[32/64]0[0/2]0HM-[3S/3.7/5]-A Micro-DIMM DDR2 SDRAM Modules
3.3
Timing Characteristics
This chapter describes the AC characteristics.
3.3.1
Speed Grade Definitions
TABLE 12
Speed Grade Definition Speed Bins for DDR2-667D, DDR2-533C and DDR2-400B
This chapter contains the Speed Grade Definition tables.
Speed Grade QAG Sort Name CAS-RCD-RP latencies Parameter Clock Frequency @ CL = 3 @ CL = 4 @ CL = 5 Row Active Time Row Cycle Time RAS-CAS-Delay Row Precharge Time Symbol
DDR2-667D -3S 5-5-5 Min. 5 3.75 3 45 60 15 15 Max. 8 8 8 70000 -- -- --
DDR2-533C -3.7 4-4-4 Min. 5 3.75 3.75 45 60 15 15 Max. 8 8 8 70000 -- -- --
DDR2-400B -5 3-3-3 Min. 5 5 5 40 55 15 15 Max. 8 8 8 70000 -- -- --
Unit
Note
tCK
-- ns ns ns ns ns ns ns
1)2)3)4) 1)2)3)4) 1)2)3)4) 1)2)3)4)5) 1)2)3)4) 1)2)3)4) 1)2)3)4)
tCK tCK tCK tRAS tRC tRCD tRP
1) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode. Timings are further guaranteed for normal OCD drive strength (EMRS(1) A1 = 0) only. 2) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross. The DQS/DQS, RDQS/RDQS, input reference level is the crosspoint when in differential strobe mode 3) Inputs are not recognized as valid until VREF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ is recognized as low. 4) The output timing reference voltage level is VTT. 5) tRAS.MAX is calculated from the maximum amount of time a DDR2 device can operate without a refresh command which is equal to 9 x tREFI.
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HYS64T[32/64]0[0/2]0HM-[3S/3.7/5]-A Micro-DIMM DDR2 SDRAM Modules
3.3.2
Component AC Timing Parameters
TABLE 13
DRAM Component Timing Parameter by Speed Grade - DDR2-667
This chapter contains the AC Timing Parameters.
Parameter
Symbol
DDR2-667 Min. Max. +450 +400 0.52 0.52 8000 -- -- -- --
Unit
Note
1)2)3)4)5)6)7)8)
tAC DQS output access time from CK / CK tDQSCK Average clock high pulse width tCH.AVG Average clock low pulse width tCL.AVG Average clock period tCK.AVG tDS.BASE DQ and DM input setup time DQ and DM input hold time tDH.BASE Control & address input pulse width for each input tIPW DQ and DM input pulse width for each input tDIPW Data-out high-impedance time from CK / CK tHZ DQS/DQS low-impedance time from CK / CK tLZ.DQS DQ low impedance time from CK/CK tLZ.DQ DQS-DQ skew for DQS & associated DQ signals tDQSQ CK half pulse width tHP
DQ output access time from CK / CK DQ hold skew factor DQ/DQS output hold time from DQS Write command to DQS associated clock edges
-450 -400 0.48 0.48 3000 100 175 0.6 0.35 --
ps ps
9) 9) 10)11) 10)11)
tCK.AVG tCK.AVG
ps ps ps
12)13)14) 13)14)15)
tCK.AVG tCK.AVG
ps ps ps ps ps ps ps nCK
9)16) 9)16) 9)16) 17) 18)
tAC.MIN 2 x tAC.MIN
-- Min(tCH.ABS, tCL.ABS) --
tAC.MAX tAC.MAX tAC.MAX
240 __ 340 -- + 0.25 -- -- -- -- 0.6 -- -- -- 1.1 0.6 -- -- -- --
tQHS tQH
WL
19) 20)
tHP - tQHS
RL-1 - 0.25 0.35 0.35 0.2 0.2 0.4 0.35 200 275 0.9 0.4 2 15 WR + tnRP 7.5
DQS latching rising transition to associated clock tDQSS edges
tCK.AVG tCK.AVG tCK.AVG tCK.AVG tCK.AVG tCK.AVG tCK.AVG
ps ps
21)
tDQSH tDQSL DQS falling edge to CK setup time tDSS DQS falling edge hold time from CK tDSH Write postamble tWPST Write preamble tWPRE Address and control input setup time tIS.BASE Address and control input hold time tIH.BASE Read preamble tRPRE Read postamble tRPST CAS to CAS command delay tCCD tWR Write recovery time Auto-Precharge write recovery + precharge time tDAL Internal write to read command delay tWTR
DQS input high pulse width DQS input low pulse width
21) 21)
22)23) 23)24) 25)26) 25)27)
tCK.AVG tCK.AVG
nCK ns nCK ns
28) 29)30) 28)31)
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HYS64T[32/64]0[0/2]0HM-[3S/3.7/5]-A Micro-DIMM DDR2 SDRAM Modules
Parameter
Symbol
DDR2-667 Min. Max. -- -- -- -- -- -- -- -- 12 12 --
Unit
Note
1)2)3)4)5)6)7)8)
Internal Read to Precharge command delay Exit self-refresh to a non-read command Exit self-refresh to read command Exit precharge power-down to any valid command (other than NOP or Deselect) Exit power down to read command Exit active power-down mode to read command (slow exit, lower power) CKE minimum pulse width ( high and low pulse width) Mode register set command cycle time MRS command to ODT update delay OCD drive mode output delay Minimum time clocks remain ON after CKE asynchronously drops LOW
tRTP tXSNR tXSRD tXP tXARD tXARDS tCKE tMRD tMOD tOIT tDELAY
7.5
ns ns nCK nCK nCK nCK nCK nCK ns ns ns
28) 28)
tRFC +10
200 2 2 7 - AL 3 2 0 0
32)
28) 28)
tIS + tCK .AVG + tIH
1) For details and notes see the relevant Qimonda component data sheet 2) VDDQ = 1.8 V 0.1V; VDD = 1.8 V 0.1 V. See notes 5)6)7)8) 3) Timing that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be powered down and then restarted through the specified initialization sequence before normal operation can continue. 4) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode. 5) The CK / CK input reference level (for timing reference to CK / CK) is the point at which CK and CK cross. The DQS / DQS, RDQS / RDQS, input reference level is the crosspoint when in differential strobe mode. 6) Inputs are not recognized as valid until VREF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ is recognized as low. 7) The output timing reference voltage level is VTT. 8) New units, `tCK.AVG` and `nCK`, are introduced in DDR2-667 and DDR2-800. Unit `tCK.AVG` represents the actual tCK.AVG of the input clock under operation. Unit `nCK` represents one clock cycle of the input clock, counting the actual clock edges. Note that in DDR2-400 and DDR2-533, `tCK` is used for both concepts. Example: tXP = 2 [nCK] means; if Power Down exit is registered at Tm, an Active command may be registered at Tm + 2, even if (Tm + 2 - Tm) is 2 x tCK.AVG + tERR.2PER(Min). 9) When the device is operated with input clock jitter, this parameter needs to be derated by the actual tERR(6-10per) of the input clock. (output deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR2-667 SDRAM has tERR(6-10PER).MIN = - 272 ps and tERR(6- 10PER).MAX = + 293 ps, then tDQSCK.MIN(DERATED) = tDQSCK.MIN - tERR(6-10PER).MAX = - 400 ps - 293 ps = - 693 ps and tDQSCK.MAX(DERATED) = tDQSCK.MAX - tERR(6-10PER).MIN = 400 ps + 272 ps = + 672 ps. Similarly, tLZ.DQ for DDR2-667 derates to tLZ.DQ.MIN(DERATED) = - 900 ps - 293 ps = - 1193 ps and tLZ.DQ.MAX(DERATED) = 450 ps + 272 ps = + 722 ps. (Caution on the MIN/MAX usage!) 10) Input clock jitter spec parameter. These parameters are referred to as 'input clock jitter spec parameters' and these parameters apply to DDR2-667 and DDR2-800 only. The jitter specified is a random jitter meeting a Gaussian distribution. 11) These parameters are specified per their average values, however it is understood that the relationship between the average timing and the absolute instantaneous timing holds all the times (min. and max of SPEC values are to be used for calculations ). 12) Input waveform timing tDS with differential data strobe enabled MR[bit10] = 0, is referenced from the input signal crossing at the VIH.AC level to the differential data strobe crosspoint for a rising signal, and from the input signal crossing at the VIL.AC level to the differential data strobe crosspoint for a falling signal applied to the device under test. DQS, DQS signals must be monotonic between Vil(DC)MAX and Vih(DC)MIN. See Figure 3. 13) If tDS or tDH is violated, data corruption may occur and the data must be re-written with valid data before a valid READ can be executed. 14) These parameters are measured from a data signal ((L/U)DM, (L/U)DQ0, (L/U)DQ1, etc.) transition edge to its respective data strobe signal ((L/U/R)DQS / DQS) crossing. 15) Input waveform timing tDH with differential data strobe enabled MR[bit10] = 0, is referenced from the differential data strobe crosspoint to the input signal crossing at the VIH.DC level for a falling signal and from the differential data strobe crosspoint to the input signal crossing at the VIL.DC level for a rising signal applied to the device under test. DQS, DQS signals must be monotonic between VIL.DC.MAX and VIH.DC.MIN. See Figure 3.
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16) tHZ and tLZ transitions occur in the same access time as valid data transitions. These parameters are referenced to a specific voltage level which specifies when the device output is no longer driving (tHZ), or begins driving (tLZ) . 17) tDQSQ: Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers as well as output slew rate mismatch between DQS / DQS and associated DQ in any given cycle. 18) tHP is the minimum of the absolute half period of the actual input clock. tHP is an input parameter but not an input specification parameter. It is used in conjunction with tQHS to derive the DRAM output timing tQH. The value to be used for tQH calculation is determined by the following equation; tHP = MIN (tCH.ABS, tCL.ABS), where, tCH.ABS is the minimum of the actual instantaneous clock high time; tCL.ABS is the minimum of the actual instantaneous clock low time. 19) tQHS accounts for: 1) The pulse duration distortion of on-chip clock circuits, which represents how well the actual tHP at the input is transferred to the output; and 2) The worst case push-out of DQS on one transition followed by the worst case pull-in of DQ on the next transition, both of which are independent of each other, due to data pin skew, output pattern effects, and pchannel to n-channel variation of the output drivers. 20) tQH = tHP - tQHS, where: tHP is the minimum of the absolute half period of the actual input clock; and tQHS is the specification value under the max column. {The less half-pulse width distortion present, the larger the tQH value is; and the larger the valid data eye will be.} Examples: 1) If the system provides tHP of 1315 ps into a DDR2-667 SDRAM, the DRAM provides tQH of 975 ps minimum. 2) If the system provides tHP of 1420 ps into a DDR2-667 SDRAM, the DRAM provides tQH of 1080 ps minimum. 21) These parameters are measured from a data strobe signal ((L/U/R)DQS / DQS) crossing to its respective clock signal (CK / CK) crossing. The spec values are not affected by the amount of clock jitter applied (i.e. tJIT.PER, tJIT.CC, etc.), as these are relative to the clock signal crossing. That is, these parameters should be met whether clock jitter is present or not. 22) Input waveform timing is referenced from the input signal crossing at the VIH.AC level for a rising signal and VIL.AC for a falling signal applied to the device under test. See Figure 4. 23) These parameters are measured from a command/address signal (CKE, CS, RAS, CAS, WE, ODT, BA0, A0, A1, etc.) transition edge to its respective clock signal (CK / CK) crossing. The spec values are not affected by the amount of clock jitter applied (i.e. tJIT.PER, tJIT.CC, etc.), as the setup and hold are relative to the clock signal crossing that latches the command/address. That is, these parameters should be met whether clock jitter is present or not. 24) Input waveform timing is referenced from the input signal crossing at the VIL.DC level for a rising signal and VIH.DC for a falling signal applied to the device under test. See Figure 4. 25) tRPST end point and tRPRE begin point are not referenced to a specific voltage level but specify when the device output is no longer driving (tRPST), or begins driving (tRPRE). Figure 2 shows a method to calculate these points when the device is no longer driving (tRPST), or begins driving (tRPRE) by measuring the signal at two different voltages. The actual voltage measurement points are not critical as long as the calculation is consistent. 26) When the device is operated with input clock jitter, this parameter needs to be derated by the actual tJIT.PER of the input clock. (output deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR2-667 SDRAM has tJIT.PER.MIN = - 72 ps and tJIT.PER.MAX = + 93 ps, then tRPRE.MIN(DERATED) = tRPRE.MIN + tJIT.PER.MIN = 0.9 x tCK.AVG - 72 ps = + 2178 ps and tRPRE.MAX(DERATED) = tRPRE.MAX + tJIT.PER.MAX = 1.1 x tCK.AVG + 93 ps = + 2843 ps. (Caution on the MIN/MAX usage!). 27) When the device is operated with input clock jitter, this parameter needs to be derated by the actual tJIT.DUTY of the input clock. (output deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR2-667 SDRAM has tJIT.DUTY.MIN = - 72 ps and tJIT.DUTY.MAX = + 93 ps, then tRPST.MIN(DERATED) = tRPST.MIN + tJIT.DUTY.MIN = 0.4 x tCK.AVG - 72 ps = + 928 ps and tRPST.MAX(DERATED) = tRPST.MAX + tJIT.DUTY.MAX = 0.6 x tCK.AVG + 93 ps = + 1592 ps. (Caution on the MIN/MAX usage!). 28) For these parameters, the DDR2 SDRAM device is characterized and verified to support tnPARAM = RU{tPARAM / tCK.AVG}, which is in clock cycles, assuming all input clock jitter specifications are satisfied. For example, the device will support tnRP = RU{tRP / tCK.AVG}, which is in clock cycles, if all input clock jitter specifications are met. This means: For DDR2-667 5-5-5, of which tRP = 15 ns, the device will support tnRP = RU{tRP / tCK.AVG} = 5, i.e. as long as the input clock jitter specifications are met, Precharge command at Tm and Active command at Tm + 5 is valid even if (Tm + 5 - Tm) is less than 15 ns due to input clock jitter. 29) DAL = WR + RU{tRP(ns) / tCK(ns)}, where RU stands for round up. WR refers to the tWR parameter stored in the MRS. For tRP, if the result of the division is not already an integer, round up to the next highest integer. tCK refers to the application clock period. Example: For DDR2-533 at tCK = 3.75 ns with tWR programmed to 4 clocks. tDAL = 4 + (15 ns / 3.75 ns) clocks = 4 + (4) clocks = 8 clocks. 30) tDAL.nCK = WR [nCK] + tnRP.nCK = WR + RU{tRP [ps] / tCK.AVG[ps] }, where WR is the value programmed in the EMR. 31) tWTR is at lease two clocks (2 x tCK) independent of operation frequency. 32) tCKE.MIN of 3 clocks means CKE must be registered on three consecutive positive clock edges. CKE must remain at the valid input level the entire time it takes to achieve the 3 clocks of registration. Thus, after any CKE transition, CKE may not transition from its valid level during the time period of tIS + 2 x tCK + tIH.
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FIGURE 2
Method for calculating transitions and endpoint
FIGURE 3
Differential input waveform timing - tDS and tDS
FIGURE 4
Differential input waveform timing - tlS and tlH
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TABLE 14
DRAM Component Timing Parameter by Speed Grade - DDR2-533
Parameter Symbol DDR2-533 Min. DQ output access time from CK / CK CAS A to CAS B command period CK, CK high-level width CKE minimum high and low pulse width CK, CK low-level width Auto-Precharge write recovery + precharge time Minimum time clocks remain ON after CKE asynchronously drops LOW DQ and DM input hold time (differential data strobe) Max. +500 -- 0.55 -- 0.55 -- -- -- -- -- +450 -- 300 + 0.25 -- -- -- -- ps Unit Note
1)2)3)4)5)6)7)
tAC tCCD tCH tCKE tCL tDAL tDELAY tDH(base)
-500 2 0.45 3 0.45 WR + tRP
tCK tCK tCK tCK tCK
ns ps ps
8)18)
tIS + tCK + tIH
225 -25 0.35 -450 0.35 -- - 0.25 100 -25 0.2 0.2 MIN. (tCL, tCH) -- 375 0.6 250 2 x tAC.MIN
9)
10)
DQ and DM input hold time (single ended data tDH1(base) strobe) DQ and DM input pulse width (each input) DQS output access time from CK / CK DQS input low (high) pulse width (write cycle) DQS-DQ skew (for DQS & associated DQ signals) Write command to 1st DQS latching transition DQ and DM input setup time (differential data strobe)
11)
tDIPW tDQSCK tDQSL,H tDQSQ tDQSS tDS(base)
tCK
ps
tCK
ps
11)
tCK
ps ps
11)
DQ and DM input setup time (single ended data tDS1(base) strobe) DQS falling edge hold time from CK (write cycle) Clock half period Data-out high-impedance time from CK / CK Address and control input hold time Address and control input pulse width (each input) Address and control input setup time DQ low-impedance time from CK / CK DQS low-impedance from CK / CK Mode register set command cycle time OCD drive mode output delay Data output hold time from DQS Data hold skew factor
11)
tDSH
tCK tCK
--
12) 13) 11)
DQS falling edge to CK setup time (write cycle) tDSS
tHP tHZ tIH(base) tIPW tIS(base) tLZ(DQ) tLZ(DQS) tMRD tOIT tQH tQHS
tAC.MAX
-- -- --
ps ps
tCK
ps ps ps
11) 14) 14)
tAC.MIN
2 0
tAC.MAX tAC.MAX
-- 12 -- 400
tCK
ns -- ps
tHP -tQHS
--
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Parameter
Symbol
DDR2-533 Min. Max. 7.8 3.9 -- -- -- 1.1 0.60 -- -- -- -- 0.60 -- -- -- -- -- -- -- --
Unit
Note
1)2)3)4)5)6)7)
Average periodic refresh Interval Auto-Refresh to Active/Auto-Refresh command period Precharge-All (4 banks) command period Precharge-All (8 banks) command period Read preamble Read postamble Active bank A to Active bank B command period Internal Read to Precharge command delay Write preamble Write postamble Write recovery time for write without AutoPrecharge Write recovery time for write with AutoPrecharge Internal Write to Read command delay Exit power down to any valid command (other than NOP or Deselect) Exit active power-down mode to Read command (slow exit, lower power) Exit precharge power-down to any valid command (other than NOP or Deselect) Exit Self-Refresh to non-Read command Exit Self-Refresh to Read command
tREFI tRFC tRP tRP tRPRE tRPST tRRD tRTP tWPRE tWPST tWR
WR
-- -- 105
s s ns ns ns
14)15) 16)18) 17)
tRP + 1tCK
15 + 1tCK 0.9 0.40 7.5 10 7.5 0.25 0.40 15
tCK tCK
ns ns ns
14) 14) 14)18) 16)20)
tCK tCK
ns
19)
tWR/tCK
7.5 2 6 - AL 2
tCK
ns
20)
tWTR tXARD tXARDS tXP tXSNR tXSRD
21) 22)
tCK tCK tCK
ns
22)
tRFC +10
200
tCK
1) For details and notes see the relevant Qimonda component data sheet 2) VDDQ = 1.8 V 0.1 V; VDD = 1.8 V 0.1 V. See notes 5)6)7)8) 3) Timing that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be powered down and then restarted through the specified initialization sequence before normal operation can continue. 4) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode. 5) The CK / CK input reference level (for timing reference to CK / CK) is the point at which CK and CK cross. The DQS / DQS, RDQS/ RDQS, input reference level is the crosspoint when in differential strobe mode. 6) Inputs are not recognized as valid until VREF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ is recognized as low. 7) The output timing reference voltage level is VTT. 8) For each of the terms, if not already an integer, round to the next highest integer. tCK refers to the application clock period. WR refers to the WR parameter stored in the MR. 9) The clock frequency is allowed to change during self-refresh mode or precharge power-down mode. 10) For timing definition, refer to the Component data sheet. 11) Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers as well as output Slew Rate mis-match between DQS / DQS and associated DQ in any given cycle. 12) MIN (tCL, tCH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this value can be greater than the minimum specification limits for tCL and tCH).
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13) The tHZ, tRPST and tLZ, tRPRE parameters are referenced to a specific voltage level, which specify when the device output is no longer driving (tHZ, tRPST), or begins driving (tLZ, tRPRE). tHZ and tLZ transitions occur in the same access time windows as valid data transitions.These parameters are verified by design and characterization, but not subject to production test. 14) The Auto-Refresh command interval has be reduced to 3.9 s when operating the DDR2 DRAM in a temperature range between 85 C and 95 C. 15) 0 C TCASE 85 C 16) 85 C < TCASE 95 C 17) A maximum of eight Auto-Refresh commands can be posted to any given DDR2 SDRAM device. 18) The tRRD timing parameter depends on the page size of the DRAM organization. See Table 2 "Ordering Informationfor RoHS Compliant Products" on Page 4. 19) The maximum limit for the tWPST parameter is not a device limit. The device operates with a greater value for this parameter, but system performance (bus turnaround) degrades accordingly. 20) WR must be programmed to fulfill the minimum requirement for the tWR timing parameter, where WRMIN[cycles] = tWR(ns)/tCK(ns) rounded up to the next integer value. tDAL = WR + (tRP/tCK). For each of the terms, if not already an integer, round to the next highest integer. tCK refers to the application clock period. WR refers to the WR parameter stored in the MRS. 21) Minimum tWTR is two clocks when operating the DDR2-SDRAM at frequencies 200 MHz. 22) User can choose two different active power-down modes for additional power saving via MRS address bit A12. In "standard active powerdown mode" (MR, A12 = "0") a fast power-down exit timing tXARD can be used. In "low active power-down mode" (MR, A12 ="1") a slow power-down exit timing tXARDS has to be satisfied.
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TABLE 15
DRAM Component Timing Parameter by Speed Grade - DDR2-400
Parameter Symbol DDR2-400 Min. DQ output access time from CK / CK CAS A to CAS B command period CK, CK high-level width CKE minimum high and low pulse width CK, CK low-level width Auto-Precharge write recovery + precharge time Minimum time clocks remain ON after CKE asynchronously drops LOW DQ and DM input hold time (differential data strobe) Max. +600 -- 0.55 -- 0.55 -- -- -- -- -- +500 -- 350 + 0.25 -- -- -- -- ps Unit Note
1)2)3)4)5)6)7)
tAC tCCD tCH tCKE tCL tDAL tDELAY tDH(base)
-600 2 0.45 3 0.45 WR + tRP
tCK tCK tCK tCK tCK
ns ps ps
8)22)
tIS + tCK + tIH
275 -25 0.35 -500 0.35 -- - 0.25 150 -25 0.2 0.2 MIN. (tCL, tCH) -- 475 0.6 350 2 x tAC.MIN
9)
10)
DQ and DM input hold time (single ended data tDH1(base) strobe) DQ and DM input pulse width (each input) DQS output access time from CK / CK DQS input low (high) pulse width (write cycle) DQS-DQ skew (for DQS & associated DQ signals) DQ and DM input setup time (differential data strobe) DQ and DM input setup time (single ended data strobe) DQS falling edge hold time from CK (write cycle) Clock half period Data-out high-impedance time from CK / CK Address and control input hold time Address and control input pulse width (each input) Address and control input setup time DQ low-impedance time from CK / CK DQS low-impedance from CK / CK Mode register set command cycle time OCD drive mode output delay Data output hold time from DQS Data hold skew factor
11)
tDIPW tDQSCK tDQSL,H tDQSQ
tCK
ps
tCK
ps
11)
Write command to 1st DQS latching transition tDQSS
tCK
ps ps
11)
tDS(base) tDS1(base) tDSH
11)
tCK tCK
--
12) 13) 11)
DQS falling edge to CK setup time (write cycle) tDSS
tHP tHZ tIH(base) tIPW tIS(base) tLZ(DQ) tLZ(DQS) tMRD tOIT tQH tQHS
tAC.MAX
-- -- --
ps ps
tCK
ps ps ps
11) 14) 14)
tAC.MIN
2 0
tAC.MAX tAC.MAX
-- 12 -- 450
tCK
ns -- ps
tHP -tQHS
--
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Parameter
Symbol
DDR2-400 Min. Max. 7.8 3.9 -- -- -- 1.1 0.60 -- -- -- -- 0.60 -- -- -- -- -- -- -- --
Unit
Note
1)2)3)4)5)6)7)
Average periodic refresh Interval Auto-Refresh to Active/Auto-Refresh command period Precharge-All (4 banks) command period Precharge-All (8 banks) command period Read preamble Read postamble Active bank A to Active bank B command period Internal Read to Precharge command delay Write preamble Write postamble Write recovery time for write without AutoPrecharge Write recovery time for write with AutoPrecharge Internal Write to Read command delay Exit power down to any valid command (other than NOP or Deselect) Exit active power-down mode to Read command (slow exit, lower power) Exit precharge power-down to any valid command (other than NOP or Deselect) Exit Self-Refresh to non-Read command Exit Self-Refresh to Read command
tREFI
-- -- 105
s s ns ns ns
14)15) 16)18) 17)
tRP tRP tRPRE tRPST tRRD tRTP tWPRE tWPST tWR
WR
tRP + 1tCK
15 + 1tCK 0.9 0.40 7.5 10 7.5 0.25 0.40 15
tCK tCK
ns ns ns
14) 14) 14)18) 16)20)
tCK tCK
ns
19)
tWR/tCK
10 2 6 - AL 2
tCK
ns
20)
tWTR tXARD tXARDS tXP tXSNR tXSRD
21) 22)
tCK tCK tCK
ns
22)
tRFC +10
200
tCK
1) For details and notes see the relevant Qimonda component data sheet 2) VDDQ = 1.8 V 0.1 V; VDD = 1.8 V 0.1 V. See notes 5)6)7)8) 3) Timing that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be powered down and then restarted through the specified initialization sequence before normal operation can continue. 4) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode. 5) The CK / CK input reference level (for timing reference to CK / CK) is the point at which CK and CK cross. The DQS / DQS, RDQS/ RDQS, input reference level is the crosspoint when in differential strobe mode. 6) Inputs are not recognized as valid until VREF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ is recognized as low. 7) The output timing reference voltage level is VTT. 8) For each of the terms, if not already an integer, round to the next highest integer. tCK refers to the application clock period. WR refers to the WR parameter stored in the MR. 9) The clock frequency is allowed to change during self-refresh mode or precharge power-down mode. 10) For timing definition, refer to the Component data sheet. 11) Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers as well as output Slew Rate mis-match between DQS / DQS and associated DQ in any given cycle. 12) MIN (tCL, tCH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this value can be greater than the minimum specification limits for tCL and tCH).
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13) The tHZ, tRPST and tLZ, tRPRE parameters are referenced to a specific voltage level, which specify when the device output is no longer driving (tHZ, tRPST), or begins driving (tLZ, tRPRE). tHZ and tLZ transitions occur in the same access time windows as valid data transitions.These parameters are verified by design and characterization, but not subject to production test. 14) The Auto-Refresh command interval has be reduced to 3.9 s when operating the DDR2 DRAM in a temperature range between 85 C and 95 C. 15) 0 C TCASE 85 C 16) 85 C < TCASE 95 C 17) A maximum of eight Auto-Refresh commands can be posted to any given DDR2 SDRAM device. 18) The tRRD timing parameter depends on the page size of the DRAM organization. See Table 2 "Ordering Informationfor RoHS Compliant Products" on Page 4. 19) The maximum limit for the tWPST parameter is not a device limit. The device operates with a greater value for this parameter, but system performance (bus turnaround) degrades accordingly. 20) WR must be programmed to fulfill the minimum requirement for the tWR timing parameter, where WRMIN[cycles] = tWR(ns)/tCK(ns) rounded up to the next integer value. tDAL = WR + (tRP/tCK). For each of the terms, if not already an integer, round to the next highest integer. tCK refers to the application clock period. WR refers to the WR parameter stored in the MRS. 21) Minimum tWTR is two clocks when operating the DDR2-SDRAM at frequencies 200 MHz. 22) User can choose two different active power-down modes for additional power saving via MRS address bit A12. In "standard active powerdown mode" (MR, A12 = "0") a fast power-down exit timing tXARD can be used. In "low active power-down mode" (MR, A12 ="1") a slow power-down exit timing tXARDS has to be satisfied.
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3.3.3
ODT AC Electrical Characteristics
TABLE 16
ODT AC Character. and Operating Conditions for DDR2-667
This chapter contains the ODT AC electrical characteristic tables.
Symbol
Parameter / Condition
Values Min. Max. 2
Unit
Note
tAOND tAON tAONPD tAOFD tAOF tAOFPD tANPD tAXPD
ODT turn-on delay ODT turn-on ODT turn-on (Power-Down Modes) ODT turn-off delay ODT turn-off ODT turn-off (Power-Down Modes) ODT to Power Down Mode Entry Latency ODT Power Down Exit Latency
2
nCK ns ns nCK ns ns nCK nCK
1) 1)2) 1) 1) 1)3) 1) 1) 1)
tAC.MIN tAC.MIN + 2 ns
2.5
tAC.MAX + 0.7 ns 2 tCK + tAC.MAX + 1 ns
2.5
tAC.MIN tAC.MIN + 2 ns
3 8
tAC.MAX + 0.6 ns 2.5 tCK + tAC.MAX + 1 ns
-- --
1) New units, 'tCK.AVG' and 'nCK', are introduced in DDR2-667 and DDR2-800. Unit 'tCK.AVG' represents the actual tCK.AVG of the input clock under operation. Unit 'nCK' represents one clock cycle of the input clock, counting the actual clock edges. Note that in DDR2-400 and DDR2-533, 'tCK' is used for both concepts. Example: tXP = 2 [nCK] means; if Power Down exit is registered at Tm, an Active command may be registered at Tm + 2, even if (Tm + 2 - Tm) is 2 x tCK.AVG+ tEPR.2PER(MIN). 2) ODT turn on time min is when the device leaves high impedance and ODT resistance begins to turn on. ODT turn on time max is when the ODT resistance is fully on. Both are measured from tAOND, which is interpreted differently per speed bin. For DDR2-667/800, tAOND is 2 clock cycles after the clock edge that registered a first ODT HIGH counting the actual input clock edges. 3) ODT turn off time min. is when the device starts to turn off ODT resistance. ODT turn off time max is when the bus is in high impedance. Both are measured from tAOFD. Both are measured from tAOFD, which is interpreted differently per speed bin. For DDR2-667/800,if tCK.AVG = 3 ns is assumed, tAOFD= 1.5 ns (0.5 x 3 ns) after the second trailing clock edge counting from the clock edge that registered a first ODT LOW and by counting the actual input clock edge.
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HYS64T[32/64]0[0/2]0HM-[3S/3.7/5]-A Micro-DIMM DDR2 SDRAM Modules
TABLE 17
ODT AC Character. and Operating Conditions for DDR2-533 & DDR2-400
Symbol Parameter / Condition Values Min. Max. 2 Unit Note
tAOND tAON tAONPD tAOFD tAOF tAOFPD tANPD tAXPD
ODT turn-on delay ODT turn-on ODT turn-on (Power-Down Modes) ODT turn-off delay ODT turn-off ODT turn-off (Power-Down Modes) ODT to Power Down Mode Entry Latency ODT Power Down Exit Latency
2
tCK
ns ns
1)
tAC.MIN tAC.MIN + 2 ns
2.5
tAC.MAX + 1 ns 2 tCK + tAC.MAX + 1 ns
2.5
tCK
ns ns
2)
tAC.MIN tAC.MIN + 2 ns
3 8
tAC.MAX + 0.6 ns 2.5 tCK + tAC.MAX + 1 ns
-- --
tCK tCK
1) ODT turn on time min is when the device leaves high impedance and ODT resistance begins to turn on. ODT turn on time max is when the ODT resistance is fully on. Both are measured from tAOND, which is interpreted differently per speed bin. For DDR2-400/533, tAOND is 10 ns (= 2 x 5 ns) after the clock edge that registered a first ODT HIGH if tCK = 5 ns. 2) ODT turn off time min. is when the device starts to turn off ODT resistance. ODT turn off time max is when the bus is in high impedance. Both are measured from tAOFD. Both are measured from tAOFD, which is interpreted differently per speed bin. For DDR2-400/533, tAOFD is 12.5 ns (= 2.5 x 5 ns) after the clock edge that registered a first ODT HIGH if tCK = 5 ns.
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Internet Data Sheet
HYS64T[32/64]0[0/2]0HM-[3S/3.7/5]-A Micro-DIMM DDR2 SDRAM Modules
3.4
IDD Specifications and Conditions
TABLE 18
IDD Measurement Conditions
This chapter describes the IDD Specifications and Conditions.
Parameter
Symbol Note
1)2)3)4)5)
Operating Current 0 IDD0 One bank Active - Precharge; tCK = tCK.MIN, tRC = tRC.MIN, tRAS = tRAS.MIN, CKE is HIGH, CS is HIGH between valid commands. Address and control inputs are SWITCHING, Databus inputs are SWITCHING. Operating Current 1 One bank Active - Read - Precharge; IOUT = 0 mA, BL = 4, tCK = tCK.MIN, tRC = tRC.MIN, tRAS = tRAS.MIN, tRCD = tRCD.MIN, AL = 0, CL = CLMIN; CKE is HIGH, CS is HIGH between valid commands. Address and control inputs are SWITCHING, Databus inputs are SWITCHING.
IDD1
6)
Precharge Standby Current IDD2N All banks idle; CS is HIGH; CKE is HIGH; tCK = tCK.MIN; Other control and address inputs are SWITCHING, Databus inputs are SWITCHING. Precharge Power-Down Current Other control and address inputs are STABLE, Data bus inputs are FLOATING. Precharge Quiet Standby Current All banks idle; CS is HIGH; CKE is HIGH; tCK = tCK.MIN; Other control and address inputs are STABLE, Data bus inputs are FLOATING. Active Standby Current Burst Read: All banks open; Continuous burst reads; BL = 4; AL = 0, CL = CLMIN; tCK = tCK.MIN; tRAS = tRAS.MAX, tRP = tRP.MIN; CKE is HIGH, CS is HIGH between valid commands. Address inputs are SWITCHING; Data Bus inputs are SWITCHING; IOUT = 0 mA.
IDD2P IDD2Q
IDD3N
Active Power-Down Current IDD3P(0) All banks open; tCK = tCK.MIN, CKE is LOW; Other control and address inputs are STABLE, Data bus inputs are FLOATING. MRS A12 bit is set to LOW (Fast Power-down Exit); Active Power-Down Current IDD3P(1) All banks open; tCK = tCK.MIN, CKE is LOW; Other control and address inputs are STABLE, Data bus inputs are FLOATING. MRS A12 bit is set to HIGH (Slow Power-down Exit); Operating Current - Burst Read IDD4R All banks open; Continuous burst reads; BL = 4; AL = 0, CL = CLMIN; tCK = tCKMIN; tRAS = tRASMAX; tRP = tRPMIN; CKE is HIGH, CS is HIGH between valid commands; Address inputs are SWITCHING; Data bus inputs are SWITCHING; IOUT = 0mA. Operating Current - Burst Write All banks open; Continuous burst writes; BL = 4; AL = 0, CL = CLMIN; tCK = tCK.MIN; tRAS = tRAS.MAX., tRP = tRP.MAX; CKE is HIGH, CS is HIGH between valid commands. Address inputs are SWITCHING; Data Bus inputs are SWITCHING; Burst Refresh Current tCK = tCK.MIN., Refresh command every tRFC = tRFC.MIN interval, CKE is HIGH, CS is HIGH between valid commands, Other control and address inputs are SWITCHING, Data bus inputs are SWITCHING. Distributed Refresh Current tCK = tCK.MIN., Refresh command every tRFC = tREFI interval, CKE is LOW and CS is HIGH between valid commands, Other control and address inputs are SWITCHING, Data bus inputs are SWITCHING.
6)
IDD4W
IDD5B
IDD5D
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HYS64T[32/64]0[0/2]0HM-[3S/3.7/5]-A Micro-DIMM DDR2 SDRAM Modules
Parameter
Symbol Note
1)2)3)4)5)
Self-Refresh Current IDD6 CKE 0.2 V; external clock off, CK and CK at 0 V; Other control and address inputs are FLOATING, Data bus inputs are FLOATING. IDD6 current values are guaranteed up to TCASE of 85 C max. All Bank Interleave Read Current IDD7 All banks are being interleaved at minimum tRC without violating tRRD using a burst length of 4. Control and address bus inputs are STABLE during DESELECTS. Iout = 0 mA. 1) VDDQ = 1.8 V 0.1 V; VDD = 1.8 V 0.1 V 2) IDD specifications are tested after the device is properly initialized and IDD parameter are specified with ODT disabled. 3) Definitions for IDD see Table 19 4) For two rank modules: for all active current measurements the other rank is in Precharge Power-Down Mode IDD2P
6)
5) For details and notes see the relevant Qimonda component data sheet 6) IDD1, IDD4R and IDD7 current measurements are defined with the outputs disabled (IOUT = 0 mA). To achieve this on module level the output buffers can be disabled using an EMRS(1) (Extended Mode Register Command) by setting A12 bit to HIGH.
TABLE 19
Definitions for IDD
Parameter LOW STABLE FLOATING SWITCHING Description
VIN VIL(ac).MAX, HIGH is defined as VIN VIH(ac).MIN
Inputs are stable at a HIGH or LOW level Inputs are VREF = VDDQ /2 Inputs are changing between HIGH and LOW every other clock (once per 2 cycles) for address and control signals, and inputs changing between HIGH and LOW every other data transfer (once per cycle) for DQ signals not including mask or strobes
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Internet Data Sheet
HYS64T[32/64]0[0/2]0HM-[3S/3.7/5]-A Micro-DIMM DDR2 SDRAM Modules
TABLE 20
IDD Specification for HYS64T[32000/64020]HM-3S-A
HYS64T32000HM-3S-A Product Type HYS64T64020HM-3S-A Unit Note1)
Organization
256MB 1 Rank x64 -3S
512MB 2 Ranks x64 -3S Max. 380 440 400 40 320 400 150 50 620 700 580 50 40 930 mA mA mA mA mA mA mA mA mA mA mA mA mA mA
2) 2) 3) 3) 3) 3) 3) 3) 2) 2) 2) 3)4) 3)4) 2)
Symbol
Max. 360 420 200 20 160 200 80 20 600 680 560 20 20 910
IDD0 IDD1 IDD2N IDD2P IDD2Q IDD3N IDD3P( MRS = 0) IDD3P( MRS = 1) IDD4R IDD4W IDD5B IDD5D IDD6 IDD7
1) 2) 3) 4)
Calculated values from component data. ODT disabled. IDD1, IDD4R and IDD7 are defined with the outputs disabled The other rank is in IDD2P Precharge Power-Down Standby Current mode Both ranks are in the same IDD mode Values for 0 C TCASE 85 C
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HYS64T[32/64]0[0/2]0HM-[3S/3.7/5]-A Micro-DIMM DDR2 SDRAM Modules
TABLE 21
IDD Specification for HYS64T[32000/64020]HM-3.7-A
HYS64T32000HM-3.7-A HYS64T64020HM-3.7-A Product Type Unit Note1)
Organization
256 MB 1 Rank x64 -3.7
512 MB 2 Ranks x64 -3.7 Max. 340 380 320 30 240 320 130 40 420 460 540 50 32 mA mA mA mA mA mA mA mA mA mA mA mA mA
2) 2) 3) 3) 3) 3) 3) 3) 2) 2) 2) 3)4) 3)4) 2)
Symbol
Max. 320 360 160 20 120 160 60 20 400 440 520 20 16 880
IDD0 IDD1 IDD2N IDD2P IDD2Q IDD3N IDD3P( MRS = 0) IDD3P( MRS = 1) IDD4R IDD4W IDD5B IDD5D IDD6 IDD7
1) 2) 3) 4)
900 mA Calculated values from component data. ODT disabled. IDD1, IDD4R and IDD7 are defined with the outputs disabled The other rank is in IDD2P Precharge Power-Down Standby Current mode Both ranks are in the same IDD mode Values for 0 C TCASE 85 C
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HYS64T[32/64]0[0/2]0HM-[3S/3.7/5]-A Micro-DIMM DDR2 SDRAM Modules
TABLE 22
IDD Specification for HYS64T[32000/64020]HM-5-A
HYS64T32000HM-5-A Product Type HYS64T64020HM-5-A Unit Note1)
Organization
256 MB 1 Rank x64 -5
512 MB 2 Ranks x64 -5 Max. 300 320 30 200 280 100 40 360 380 500 50 32 mA mA mA mA mA mA mA mA mA mA mA mA mA
2) 2) 3) 3) 3) 3) 3) 3) 2) 2) 2) 3)4) 3)4) 2)
Symbol
Max. 280 300 20 100 140 50 20 340 360 480 20 16 840
IDD0 IDD1 IDD2N IDD2P IDD2Q IDD3N IDD3P( MRS = 0) IDD3P( MRS = 1) IDD4R IDD4W IDD5B IDD5D
IDD6
IDD7
1) 2) 3) 4)
860 mA Calculated values from component data. ODT disabled. IDD1, IDD4R and IDD7 are defined with the outputs disabled The other rank is in IDD2P Precharge Power-Down Standby Current mode Both ranks are in the same IDD mode Values for 0 C TCASE 85 C
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HYS64T[32/64]0[0/2]0HM-[3S/3.7/5]-A Micro-DIMM DDR2 SDRAM Modules
4
SPD Codes
This chapter lists all hexadecimal byte values stored in the EEPROM of the products described in this data sheet. SPD stands for serial presence detect. All values with XX in the table are module specific bytes which are defined during production. List of SPD Code Tables * Table 23 "SPD codes for HYS64T[32/64]0[0/2]0HM-[3S/3.7/5]-A" on Page 33
TABLE 23
SPD codes for HYS64T[32/64]0[0/2]0HM-[3S/3.7/5]-A
HYS64T32000HM-3.7-A HYS64T32000HM-3S-A HYS64T64020HM-3S-A HYS64T32000HM-5-A HYS64T64020HM-5-A 512MB x64 2 Ranks (x16) HEX 80 08 08 0D 0A 61 40 00 05 50 Product Type HYS64T64020HM-3.7-A 512MB x64
Organization
256MB x64 1 Rank (x16)
512MB x64
256MB x64
256MB x64
2 Ranks 1 Rank (x16) (x16)
2 Ranks 1 Rank (x16) (x16)
Label Code
PC2- PC2- PC2- PC2- PC2- PC2- 5300M- 5300M- 4200M- 4200M- 3200M- 3200M- 555 555 444 444 333 333 Rev. 1.2 Rev. 1.2 Rev. 1.1 Rev. 1.1 Rev. 1.1 Rev. 1.1 Description Programmed SPD Bytes in EEPROM Total number of Bytes in EEPROM Memory Type (DDR2) Number of Row Addresses DIMM Rank and Stacking Information Data Width Not used Interface Voltage Level HEX 80 08 08 0D 60 40 00 05 30 HEX 80 08 08 0D 0A 61 40 00 05 30 HEX 80 08 08 0D 0A 60 40 00 05 3D HEX 80 08 08 0D 0A 61 40 00 05 3D HEX 80 08 08 0D 0A 60 40 00 05 50
JEDEC SPD Revision Byte# 0 1 2 3 4 5 6 7 8 9
Number of Column Addresses 0A
tCK @ CLMAX (Byte 18) [ns]
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HYS64T[32/64]0[0/2]0HM-[3S/3.7/5]-A Micro-DIMM DDR2 SDRAM Modules
HYS64T32000HM-3.7-A
HYS64T32000HM-3S-A
HYS64T64020HM-3S-A
HYS64T32000HM-5-A
Organization
256MB x64 1 Rank (x16)
512MB x64
256MB x64
512MB x64
256MB x64
512MB x64 2 Ranks (x16)
2 Ranks 1 Rank (x16) (x16)
2 Ranks 1 Rank (x16) (x16)
Label Code
PC2- PC2- PC2- PC2- PC2- PC2- 5300M- 5300M- 4200M- 4200M- 3200M- 3200M- 555 555 444 444 333 333 Rev. 1.2 Rev. 1.2 Rev. 1.1 Rev. 1.1 Rev. 1.1 Rev. 1.1 Description [ns] HEX HEX 45 00 82 10 00 00 0C 04 38 01 08 00 03 3D 50 50 60 3C 28 3C 2D HEX 50 00 82 10 00 00 0C 04 38 00 08 00 01 3D 50 50 60 3C 28 3C 2D HEX 50 00 82 10 00 00 0C 04 38 00 08 00 01 3D 50 50 60 3C 28 3C 2D HEX 60 00 82 10 00 00 0C 04 38 00 08 00 01 50 60 50 60 3C 28 3C 28 HEX 60 00 82 10 00 00 0C 04 38 00 08 00 01 50 60 50 60 3C 28 3C 28
JEDEC SPD Revision Byte# 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
tAC SDRAM @ CLMAX (Byte 18) 45
Error Correction Support (non- 00 ECC, ECC) Refresh Rate and Type Primary SDRAM Width Not used Burst Length Supported Number of Banks on SDRAM Device Supported CAS Latencies DIMM Mechanical Characteristics DIMM Type Information DIMM Attributes Component Attributes 82 10 00 0C 04 38 01 08 00 03 3D 50 50 60 3C 28 3C 2D
Error Checking SDRAM Width 00
tCK @ CLMAX -1 (Byte 18) [ns] tAC SDRAM @ CLMAX -1 [ns] tCK @ CLMAX -2 (Byte 18) [ns] tAC SDRAM @ CLMAX -2 [ns] tRP.MIN [ns] tRRD.MIN [ns] tRCD.MIN [ns] tRAS.MIN [ns]
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HYS64T64020HM-5-A
Product Type
HYS64T64020HM-3.7-A
Internet Data Sheet
HYS64T[32/64]0[0/2]0HM-[3S/3.7/5]-A Micro-DIMM DDR2 SDRAM Modules
HYS64T32000HM-3.7-A
HYS64T32000HM-3S-A
HYS64T64020HM-3S-A
HYS64T32000HM-5-A
Organization
256MB x64 1 Rank (x16)
512MB x64
256MB x64
512MB x64
256MB x64
512MB x64 2 Ranks (x16)
2 Ranks 1 Rank (x16) (x16)
2 Ranks 1 Rank (x16) (x16)
Label Code
PC2- PC2- PC2- PC2- PC2- PC2- 5300M- 5300M- 4200M- 4200M- 3200M- 3200M- 555 555 444 444 333 333 Rev. 1.2 Rev. 1.2 Rev. 1.1 Rev. 1.1 Rev. 1.1 Rev. 1.1 Description Module Density per Rank HEX 40 20 27 10 17 3C 1E 1E 00 00 3C 69 80 18 22 00 72 5F 36 24 24 29 HEX 40 20 27 10 17 3C 1E 1E 00 00 3C 69 80 18 22 00 55 72 5F 36 24 24 29 HEX 40 25 37 10 22 3C 1E 1E 00 00 3C 69 80 1E 28 00 53 72 53 2B 1D 1D 23 HEX 40 25 37 10 22 3C 1E 1E 00 00 3C 69 80 1E 28 00 53 72 53 2B 1D 1D 23 HEX 40 35 47 15 27 3C 28 1E 00 00 37 69 80 23 2D 00 51 72 43 23 1D 19 1C HEX 40 35 47 15 27 3C 28 1E 00 00 37 69 80 23 2D 00 51 72 43 23 1D 19 1C
JEDEC SPD Revision Byte# 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53
tAS.MIN and tCS.MIN [ns] tAH.MIN and tCH.MIN [ns] tDS.MIN [ns] tDH.MIN [ns] tWR.MIN [ns] tWTR.MIN [ns] tRTP.MIN [ns]
Analysis Characteristics
tRC and tRFC Extension tRC.MIN [ns] tRFC.MIN [ns] tCK.MAX [ns] tDQSQ.MAX [ns] tQHS.MAX [ns]
PLL Relock Time Psi(T-A) DRAM T0 (DT0) T2N (DT2N, UDIMM) or T2Q (DT2Q, RDIMM) T2P (DT2P) T3N (DT3N) T3P.fast (DT3P fast)
TCASE.MAX Delta / T4R4W Delta 55
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HYS64T64020HM-5-A
Product Type
HYS64T64020HM-3.7-A
Internet Data Sheet
HYS64T[32/64]0[0/2]0HM-[3S/3.7/5]-A Micro-DIMM DDR2 SDRAM Modules
HYS64T32000HM-3.7-A
HYS64T32000HM-3S-A
HYS64T64020HM-3S-A
HYS64T32000HM-5-A
Organization
256MB x64 1 Rank (x16)
512MB x64
256MB x64
512MB x64
256MB x64
512MB x64 2 Ranks (x16)
2 Ranks 1 Rank (x16) (x16)
2 Ranks 1 Rank (x16) (x16)
Label Code
PC2- PC2- PC2- PC2- PC2- PC2- 5300M- 5300M- 4200M- 4200M- 3200M- 3200M- 555 555 444 444 333 333 Rev. 1.2 Rev. 1.2 Rev. 1.1 Rev. 1.1 Rev. 1.1 Rev. 1.1 Description T3P.slow (DT3P slow) T4R (DT4R) / T4R4W Sign (DT4R4W) T5B (DT5B) T7 (DT7) Psi(ca) PLL Psi(ca) REG TPLL (DTPLL) SPD Revision Checksum of Bytes 0-62 Manufacturer's JEDEC ID Code (1) Manufacturer's JEDEC ID Code (2) Manufacturer's JEDEC ID Code (3) Manufacturer's JEDEC ID Code (4) Manufacturer's JEDEC ID Code (5) Manufacturer's JEDEC ID Code (6) Manufacturer's JEDEC ID Code (7) HEX 1A 52 1E 31 00 00 00 12 D0 7F 7F 7F 7F 7F 51 00 HEX 1A 52 1E 31 00 00 00 00 12 D1 7F 7F 7F 7F 7F 51 00 HEX 16 36 1C 30 00 00 00 00 11 C0 7F 7F 7F 7F 7F 51 00 HEX 16 36 1C 30 00 00 00 00 11 C1 7F 7F 7F 7F 7F 51 00 HEX 16 2E 1A 2D 00 00 00 00 11 08 7F 7F 7F 7F 7F 51 00 HEX 16 2E 1A 2D 00 00 00 00 11 09 7F 7F 7F 7F 7F 51 00
JEDEC SPD Revision Byte# 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70
TREG (DTREG) / Toggle Rate 00
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HYS64T64020HM-5-A
Product Type
HYS64T64020HM-3.7-A
Internet Data Sheet
HYS64T[32/64]0[0/2]0HM-[3S/3.7/5]-A Micro-DIMM DDR2 SDRAM Modules
HYS64T32000HM-3.7-A
HYS64T32000HM-3S-A
HYS64T64020HM-3S-A
HYS64T32000HM-5-A
Organization
256MB x64 1 Rank (x16)
512MB x64
256MB x64
512MB x64
256MB x64
512MB x64 2 Ranks (x16)
2 Ranks 1 Rank (x16) (x16)
2 Ranks 1 Rank (x16) (x16)
Label Code
PC2- PC2- PC2- PC2- PC2- PC2- 5300M- 5300M- 4200M- 4200M- 3200M- 3200M- 555 555 444 444 333 333 Rev. 1.2 Rev. 1.2 Rev. 1.1 Rev. 1.1 Rev. 1.1 Rev. 1.1 Description Manufacturer's JEDEC ID Code (8) Product Type, Char 1 Product Type, Char 2 Product Type, Char 3 Product Type, Char 4 Product Type, Char 5 Product Type, Char 6 Product Type, Char 7 Product Type, Char 8 Product Type, Char 9 Product Type, Char 10 Product Type, Char 11 Product Type, Char 12 Product Type, Char 13 Product Type, Char 14 Product Type, Char 15 Product Type, Char 16 Product Type, Char 17 Product Type, Char 18 Module Revision Code Test Program Revision Code Module Manufacturing Date Year HEX 00 HEX 00 xx 36 34 54 36 34 30 32 30 48 4D 33 53 41 20 20 20 20 20 3x xx xx HEX 00 xx 36 34 54 33 32 30 30 30 48 4D 33 2E 37 41 20 20 20 20 5x xx xx HEX 00 xx 36 34 54 36 34 30 32 30 48 4D 33 2E 37 41 20 20 20 20 5x xx xx HEX 00 xx 36 34 54 33 32 30 30 30 48 4D 35 41 20 20 20 20 20 20 5x xx xx HEX 00 xx 36 34 54 36 34 30 32 30 48 4D 35 41 20 20 20 20 20 20 5x xx xx
JEDEC SPD Revision Byte# 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93
Module Manufacturer Location xx 36 34 54 33 32 30 30 30 48 4D 33 53 41 20 20 20 20 20 3x xx xx
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HYS64T64020HM-5-A
Product Type
HYS64T64020HM-3.7-A
Internet Data Sheet
HYS64T[32/64]0[0/2]0HM-[3S/3.7/5]-A Micro-DIMM DDR2 SDRAM Modules
HYS64T32000HM-3.7-A
HYS64T32000HM-3S-A
HYS64T64020HM-3S-A
HYS64T32000HM-5-A
Organization
256MB x64 1 Rank (x16)
512MB x64
256MB x64
512MB x64
256MB x64
512MB x64 2 Ranks (x16)
2 Ranks 1 Rank (x16) (x16)
2 Ranks 1 Rank (x16) (x16)
Label Code
PC2- PC2- PC2- PC2- PC2- PC2- 5300M- 5300M- 4200M- 4200M- 3200M- 3200M- 555 555 444 444 333 333 Rev. 1.2 Rev. 1.2 Rev. 1.1 Rev. 1.1 Rev. 1.1 Rev. 1.1 Description Module Manufacturing Date Week Module Serial Number Not used Blank for customer use HEX xx xx 00 FF HEX xx xx 00 FF HEX xx xx 00 FF HEX xx xx 00 FF HEX xx xx 00 FF HEX xx xx 00 FF
JEDEC SPD Revision Byte# 94 95 - 98 99 - 127 128 - 255
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HYS64T64020HM-5-A
Product Type
HYS64T64020HM-3.7-A
Internet Data Sheet
HYS64T[32/64]0[0/2]0HM-[3S/3.7/5]-A Micro-DIMM DDR2 SDRAM Modules
5
Package Outlines
FIGURE 5
Package Outline Raw Card A L-DIM-214-1
This chapter contains the package outlines of the products.
Notes 1. Drawing according to ISO 8015 2. Dimensions in mm 3. General tolerances +/- 0.15
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HYS64T[32/64]0[0/2]0HM-[3S/3.7/5]-A Micro-DIMM DDR2 SDRAM Modules
FIGURE 6
Package Outline Raw Card B L-DIM-214-2
Notes 1. Drawing according to ISO 8015 2. Dimensions in mm 3. General tolerances +/- 0.15
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HYS64T[32/64]0[0/2]0HM-[3S/3.7/5]-A Micro-DIMM DDR2 SDRAM Modules
6
Product Type Nomenclature
Qimonda's nomenclature uses simple coding combined with some proprietary coding. Table 24 provides examples for module and component product type number as well as the field number. The detailed field description together with possible values and coding explanation is listed for modules in Table 25 and for components in Table 26.
TABLE 24
Nomenclature Fields and Examples
Example for Field Number 1 Micro-DIMM DDR2 DRAM HYS HYB 2 64 18 3 T T 4 64/128 5 0 6 2 7 0 0 8 K A 9 M C 10 -5 -5 11 -A
512/1G 16
TABLE 25
DDR2 DIMM Nomenclature
Field 1 2 3 4 Description Qimonda Module Prefix Module Data Width [bit] DRAM Technology Memory Density per I/O [Mbit]; Module Density1) Values HYS 64 72 T 32 64 128 256 512 5 6 7 8 9 Raw Card Generation Number of Module Ranks Product Variations Package, Lead-Free Status Module Type 0 .. 9 0, 2, 4 0 .. 9 A .. Z D M R U F Coding Constant Non-ECC ECC DDR2 256 MByte 512 MByte 1 GByte 2 GByte 4 GByte Look up table 1, 2, 4 Look up table Look up table SO-DIMM Micro-DIMM Registered Unbuffered Fully Buffered
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HYS64T[32/64]0[0/2]0HM-[3S/3.7/5]-A Micro-DIMM DDR2 SDRAM Modules
Field 10
Description Speed Grade
Values -2.5F -2.5 -3 -3S -3.7 -5
Coding PC2-6400 5-5-5 PC2-6400 6-6-6 PC2-5300 4-4-4 PC2-5300 5-5-5 PC2-4200 4-4-4 PC2-3200 3-3-3 First Second
11
Die Revision
-A -B
1) Multiplying "Memory Density per I/O" with "Module Data Width" and dividing by 8 for Non-ECC and 9 for ECC modules gives the overall module memory density in MBytes as listed in column "Coding".
TABLE 26
DDR2 DRAM Nomenclature
Field 1 2 3 4 Description Qimonda Component Prefix Interface Voltage [V] DRAM Technology Component Density [Mbit] Values HYB 18 T 256 512 1G 2G 5+6 Number of I/Os 40 80 16 7 8 9 10 Product Variations Die Revision Package, Lead-Free Status Speed Grade 0 .. 9 A B C F -25F -2.5 -3 -3S -3.7 -5 Coding Constant SSTL_18 DDR2 256 Mbit 512 Mbit 1 Gbit 2 Gbit x4 x8 x16 Look up table First Second FBGA, lead-containing FBGA, lead-free DDR2-800 5-5-5 DDR2-800 6-6-6 DDR2-667 4-4-4 DDR2-667 5-5-5 DDR2-533 4-4-4 DDR2-400 3-3-3
Rev. 1.11, 2006-11 03062006-HT1R-Z2PY
42
Internet Data Sheet
HYS64T[32/64]0[0/2]0HM-[3S/3.7/5]-A Micro-DIMM DDR2 SDRAM Modules
Table of Contents
1 1.1 1.2 2 2.1 3 3.1 3.2 3.3 3.3.1 3.3.2 3.3.3 3.4 4 5 6 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DC Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Speed Grade Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Component AC Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ODT AC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDD Specifications and Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 13 14 15 15 16 26 28
SPD Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Product Type Nomenclature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Rev. 1.11, 2006-11 03062006-HT1R-Z2PY
43
Internet Data Sheet
Edition 2006-11 Published by Qimonda AG Gustav-Heinemann-Ring 212 D-81739 Munchen, Germany (c) Qimonda AG 2006. All Rights Reserved. Legal Disclaimer The information given in this Internet Data Sheet shall in no event be regarded as a guarantee of conditions or characteristics ("Beschaffenheitsgarantie"). With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Qimonda hereby disclaims any and all warranties and liabilities of any kind, including without limitation warranties of non-infringement of intellectual property rights of any third party. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Qimonda Office. Warnings Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Qimonda Office. Qimonda Components may only be used in life-support devices or systems with the express written approval of Qimonda, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. www.qimonda.com

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